- A simulation tool for hardware descriptions
See the file man1/alc_origin.1.
asimut [options] [root_file] [pattern_file] [result_file]
is a logical simulation tool for hardware descriptions. It
compiles and loads a complete hardware description written in VHDL (Very high
speed integrated circuits Hardware Description Language). The hardware
description may be structural (a hierarchy of instances) or behavioural. Only
a subset of VHDL is supported. Descriptions that do not match this subset
cause a syntax error during compilation. See vhdl(5)
information about the supported subset of VHDL.
Once a hardware description is loaded, asimut
looks for a simulation
pattern description file. This file is to be written in pat
file is compiled, loaded and linked with the hardware description. Then, the
simulation is started. When patterns are processed, a result file in
format is produced.
If a save action has been requested in the pattern description file (see pat
creates also a save file representing the state of the
description at the end of the simulation of the last pattern. The save file is
.sav, where root_file
is the name of the
The save file can be used in a later simulation sequence to initialize the state
of the (same) hardware description before the simulation begins. Using this
mechanism, a large sequence of patterns can be breaked onto several small
sequences, each one initializing the hardware description with the save file
resulted from the previous sequence.
reads several parameters from the environment variables :
- list of directories containing description and pattern
files (using $PATH syntax). The default path is the current directory (see
- specifies the current working directory. The working
directory idicates the place where all output files are written.
- Indicates the file where the behavioral description files
are listed. This file is used to leaf cells of a structural
- file extension for structural entity. (see mbk(1))
- list of file extensions for behavioural entities (using
$PATH syntax). The default file extension is vbe.
- list of file extensions for pattern description entities
(using $PATH syntax). The default file extension is pat.
- list of file extensions for delays description entities
(using $PATH syntax). The default file extension is dly.
- maximum number of errors allowed during simulation phase.
If the number of errors occured during simulation reaches VH_MAXERR,
asimut stops the simulation at the end of processing the current
pattern. Patterns following the current pattern remain unprocessed and are
reproduced in the result file. The default value of VH_MAXERR is
is the name of the description.
By default asimut
looks for a structural description. It uses the
environment variables to identify both the format and the
extension of structural description files. To load structural VHDL files
must be set to vst
To load a pure behavioural description -b
option must be specified. In
such a case asimut
loads a data flow VHDL description file. The
environment variable gives the extensions to be used.
is the entity name of the pattern description. The file
containing this entity must be named pattern_file.ext
is one of the extension specified in VH_PATSFX
is the result file produced by asimut
. The result file
is a pattern description file with the extension specified by
- consider the root_file description as a behavioural
- -backdelay [min, max, typ] delay_file
- use file delay_file.ext for delays backannotation,
where ext is one of the extension specified in
- use BDDs (Binary Decision Diagram) to represent
expressions. Using this option makes the simulation be two times faster
but increases memory requirement
- run only the compilation stage
- -core core_file
- at the first error encountered, dump the state of the
circuit in both an ascii file (suffixed .cor) and a binary save file
(suffixed .sav) which can be used as initialization file in a further
session. If the -nores option is specified a pattern file is also
- call the debugger (developper usage)
- -defaultdelay (-dd)
- only null delays (no after clause in the VHDL file) are
changed if backannotated delays or fixed delays are specified.
- -fixeddelay value (-fd value)
- all delays of the description are fixed to
- display this help file
- -i value
- initialize all signals of the description with
value. Value can be 0 or 1
- -i save_file
- read a save file and use it to initialize the state of the
description before processing the first pattern (the file name cannot be 1
- -inspect instance_name
- produce a pattern file corresponding to the interface of
the instance identified by instance-name
- -l n
- print at most n characters for pattern labels. The
default value for n is 15.
- do not generate result file
- -p n
- load at most n patterns from input pattern file each
time. Using this feature reduces memory allocation when a great number of
patterns are to be simulated. In addition after the n patterns have
been processed, the simulation result is printed in the result pattern
file. The default value for n is 0 which makes the whole pattern
file be loaded.
- trace signals when making BDDs (developper usage).
- use transport delay model (default is inertial).
- -zerodelay (-zd)
- all the delays of the VHDL description are supposed to be
asimut -b -i init_add adder_32 adder_patterns res_add
simulates a behavioural description held in the file named 'adder_32.vbe using
the pattern file `adder_patterns.pat'. The simulation results is written into
'res_add.pat' and the description is initialized with the values contained in
Register initializations in the pattern file allows changing the value of a
register into a known value. However, using this feature to initialize a
register before executing the first pattern is not recommended. Registers
value (defined by the initialization statement) may be overwritten since
description has not a coherent state before the first pattern.
vhdl(5), pat(5), genpat(1), mbk(1)
See the file man1/alc_bug_report.1.